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Viewing: ECE 464/ECE 564 : ASIC and FPGA Design with Verilog

Last approved: Sat, 14 Jan 2017 09:02:29 GMT

Last edit: Thu, 10 Nov 2016 19:51:57 GMT

Change Type
ECE (Electrical and Computer Engineering)
Dual-Level Course
Cross-listed Course
ASIC and FPGA Design with Verilog
ASIC and FPGA Design
College of Engineering
Electrical & Computer Engineering (14ECE)
Term Offering
Fall Only
Offered Every Year
Spring 2017
Previously taught as Special Topics?
Course Delivery
Face-to-Face (On Campus)
Distance Education (DELTA)

Grading Method
Graded with S/U option
Contact Hours
(Per Week)
Component TypeContact Hours
Course Attribute(s)

If your course includes any of the following competencies, check all that apply.
University Competencies

Course Is Repeatable for Credit
Paul Franzon

Open when course_delivery = campus OR course_delivery = blended OR course_delivery = flip
Enrollment ComponentPer SemesterPer SectionMultiple Sections?Comments
Lecture180180NoAll students must enroll in lecture.
Laboratory18030YesAll students must enroll in one of the lab sections.
Open when course_delivery = distance OR course_delivery = online OR course_delivery = remote
Delivery FormatPer SemesterPer SectionMultiple Sections?Comments
LEC3030NoThe instructor prefers that DE students register for ECE 564.
LAB3030NoThe students will register for a lab, but will access the required tools remotely by logging into the workstations.
P: Grade of C or better in ECE 212 or equivalent.
Is the course required or an elective for a Curriculum?
SIS Program CodeProgram TitleRequired or Elective?
14CPEBSComputer EngineeringElective
14EEBSElectrical EngineeringElective
Design of digital application specific integrated circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) based on hardware description languages (Verilog) and CAD tools. Emphasis on design practices and underlying methods. Introduction to ASIC specific design issues including verification, design for test, low power design and interfacing with memories. Required design project. Expected Prior Experience or Background: ECE 310 is useful but not assumed. Functionally, I assume that students are familiar with logic design, including combinational logic gates, sequential logic gates, timing design, Finite State Machines, etc.

1. Dual-Level Course. This course has been taught as a dual level course for a long time as ECE 464/520. But, due to the new dual-level naming requirements, 520 must be renamed as 564. Later, we will drop 520.

The differences between 464 and 565 are described in the Student Evaluation Methods section.  Specifically, 564 students are required to implement a substantially more challenging project that requires much deeper mastery of the material.

2. Title change: A recent marketing study commissioned by DELTA showed that course titles with descriptve titles and titles specifying skills gained are more successful.

3. The pre-requisites are updated to reflect recent updates to the curriculum.  Namely, 406 was removed and replaced with 310.  ECE 302 is no longer deemed a prerequisite.

4. Course catalog change: It is more descriptive of the actual course content.

5. Required for Curricula?  ECE 464 is now a specialization elective in the EE and CPE degree programs.  This was a result of the curriculum redesign circa 2013.


Is this a GEP Course?
GEP Categories

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Global Knowledge Open when gep_category = GLOBAL
Each course in the Global Knowledge category of the General Education Program will provide instruction and guidance that help students to achieve objective #1 plus at least one of objectives 2, 3, and 4:


Please complete at least 1 of the following student objectives.






US Diversity Open when gep_category = USDIV
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Please complete at least 2 of the following student objectives.








Requisites and Scheduling
a. If seats are restricted, describe the restrictions being applied.

b. Is this restriction listed in the course catalog description for the course?

List all course pre-requisites, co-requisites, and restrictive statements (ex: Jr standing; Chemistry majors only). If none, state none.

List any discipline specific background or skills that a student is expected to have prior to taking this course. If none, state none. (ex: ability to analyze historical text; prepare a lesson plan)

Additional Information
Complete the following 3 questions or attach a syllabus that includes this information. If a 400-level or dual level course, a syllabus is required.
Title and author of any required text or publications.

Major topics to be covered and required readings including laboratory and studio topics.

List any required field trips, out of class activities, and/or guest speakers.

No new resources required.

  1. To prepare the student to be an entry-level industrial standard cell ASIC or FPGA designer.

  2. To give the student an understanding of issues and tools related to ASIC/FPGA design and implementation, including timing, performance and power optimization, verification and manufacturing test.

Student Learning Outcomes

  1. Students will be able to design and synthesize a complex digital functional block, containing over 1,000 gates, using Verilog HDL and Synopsys Design Compiler. 

  2. Students will demonstrate an understanding of how to optimize the performance, area, and power of a complex digital functional block, and the tradeoffs between these.

  3. Students will demonstrate an understanding of issues involved in ASIC design, including technology choice, design management, tool-flow, verification, debug and test, as well as the impact of technology scaling on ASIC design.

Evaluation MethodWeighting/Points for EachDetails
Midterm12%75 minute midterm exam. Comprehensive, open-book, open-notes exam.
Homework25%Homeworks and Online quizzes deployed through Moodle.

The homeworks are designed to either help you gain the skills required for the project or to help prepare you for the exams. Collaboration is encouraged though each student is expected to turn in individual solutions.

Each module is broken into small segments with a quiz at the end of each segment. This quiz is simply to provide you with feedback on the knowledge and understanding you gained in that segment. These quizzes are a relatively small fraction of the Homework grade.
Quizzes5%End of module quizzes. These quizzes evaluate if you retained the material covered in each module.
Final Exam25Final Exam. Comprehensive, open-book, open-notes final exam lasting 3 hours.
Project33%A fixed project will be published for the class. The project will be executed in pairs. DE students are permitted to do the project individually. Project requirements will be somewhat relaxed for DE and ECE 464 students. An on-campus ECE 564 student can chose to do the project as an individual but requirements for such a student WON'T be relaxed.

The final project grade is based on a preliminary report (3%) and a final report (30%).
TopicTime Devoted to Each TopicActivity
Review of Digital Design2 hoursThis module quickly points out the prior knowledge assumed by this class and goes over timing diagrams and gate level design in more detail.
Introduction to ASIC Design2 hoursMoore's Law; ASIC Styles; CAD Flows
Timing2.5 hoursClock Distribution; Flip-flop and latch timing; Timing-aware design
Design of digital hardware using Verilog HDL4 hoursBasic synthesizable constructs; synthesis; verification flow; Synthesizable structures; Common Problems & Fixes; Advanced Examples
Design of Finite State Machines2 hoursTypes of Finite State Machines; Coding Style
Complexity2.5 hoursDatapath & Control; Motion Vector Example; Optimizing Performance and Area; C to Verilog
Managing Hierarchy2.5 hoursSpecifying and deciding on hierarchy
Verification2.5 hoursHow to verify correctness of modules and system-on-chip
Design for Test2 hoursIntroduction to how the design is modified to enable manufacturing test
Low Power Design2 hoursHow to do low-power design in synthesizable code
Design for FPGAs2 hoursIssues specific to FPGAs
Tricks and Techniques2 hoursSynthesis and code examples for improving design efficiency
Verilog20012 hoursBrief introduction to features in Verilog 2001 not already covered
Credit Hours: If you read through the schedule in the syllabus, you'll see that contact hours are specified for each week. If you tally up the contact hours, there are a total of 30 hours of lecture and 24 hours of self-contained lab. This comes to 2 hours/week of lecture and 1.6 hours/week of lab. Using the spreadsheet on this website, I calculate this to be 3.0 credit hours.

mlnosbis 10/19/2016: No overlapping courses.

ghodge 10/20/2016 I edited the number of students each semester to be consistent with the CIM definitions. Ready for ABGS reviewers.

ABGS Reviewer Comments:
dgyu (Wed, 21 Oct 2015 19:18:21 GMT): Rollback: Justification for additional credit hour is not sufficient. It cannot simply state that the course project substantiates the credit hour difference. The GSC needs more quantitative or concrete justifications for the additional credit hour.
mjescuti (Wed, 21 Oct 2015 19:58:31 GMT): Rollback: James, I think you need to address the concerns from the Graduate committee.
jtuck (Fri, 30 Oct 2015 18:29:30 GMT): CH is back to 3, as it was previously. We will come back and do the CH increase if we have the backing of the graduate studies committee.
dwparish (Thu, 25 Feb 2016 16:04:20 GMT): Rollback: Confusing to the committee. See Dr. Ozturk
jtuck (Fri, 18 Mar 2016 18:57:01 GMT): Rollback: Rollback for editing/review.
gbyrd (Mon, 25 Apr 2016 20:23:17 GMT): Reference to "565" instead of 564 in the Justification section.
aeherget (Fri, 23 Sep 2016 17:57:07 GMT): AECHH: Attaching updated syllabus. 9/23/2016
aeherget (Tue, 04 Oct 2016 14:48:00 GMT): AECHH: Uploading new syllabus and editing prerequisites at instructor's request via email. 10-4-2016 Explanation of credit/contact hours in Additional Comments.
Key: 1021