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Viewing: ECE 506 / CSC 406 / CSC 506 / ECE 406 : Architecture Of Parallel Computers

Last approved: Wed, 14 Mar 2018 13:50:02 GMT

Last edit: Wed, 14 Mar 2018 13:49:55 GMT

Change Type
ECE (Electrical and Computer Engineering)
Dual-Level Course
Cross-listed Course
Course Prefix:
Architecture Of Parallel Computers
Arch Parallel Comp
College of Engineering
Electrical & Computer Engineering (14ECE)
Term Offering
Fall and Spring
Offered Every Year
Spring 2017
Previously taught as Special Topics?
Course Delivery
Face-to-Face (On Campus)

Grading Method
Contact Hours
(Per Week)
Component TypeContact Hours
Course Attribute(s)

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University Competencies

Course Is Repeatable for Credit
Yan Solihin

Open when course_delivery = campus OR course_delivery = blended OR course_delivery = flip
Enrollment ComponentPer SemesterPer SectionMultiple Sections?Comments
Open when course_delivery = distance OR course_delivery = online OR course_delivery = remote
Prerequisite: ECE 310

Is the course required or an elective for a Curriculum?
The need for parallel and massively parallel computers. Taxonomy of parallel computer architecture, and programming models for parallel architectures. Example parallel algorithms. Shared-memory vs. distributed-memory architectures. Correctness and performance issues. Cache coherence and memory consistency. Bus-based and scalable directory-based multiprocessors. Interconnection-network topologies and switch design. Brief overview of advanced topics such as multiprocessor prefetching and speculative parallel execution. Credit is not allowed for more than one course in this set: ECE 406, ECE 506, CSC 406.

1. For several semesters, we have offered an undergraduate section of this course as an ECE 492, and this CAF makes that undergraduate section official. This will increase students awareness of the course and allow them to officially count it toward their major specialization electives.

2. We have modified the course learning outcomes to differentiate the expectations of ECE 406 and ECE 506 students. Course assignments and exams also reflect this difference. For example, 506 projects will include additional requirements that support their additional learning outcomes. Similarly, exams will include additional questions that evaluate these extra learning outcomes.

3. We've updated the course textbook, schedule, and syllabus to reflect how Dr. Solihin currently teaches the course.

4. ECE 506 is cross-listed as CSC 506. 

5. The pre-requisites now reflect recent changes to our curriculum (old 406 is now 310). 

6. A statement has been added to the Catalog Description indicating that students can only get credit for one of ECE 406, ECE 506 or CSC 506.


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Requisites and Scheduling
a. If seats are restricted, describe the restrictions being applied.

b. Is this restriction listed in the course catalog description for the course?

List all course pre-requisites, co-requisites, and restrictive statements (ex: Jr standing; Chemistry majors only). If none, state none.

List any discipline specific background or skills that a student is expected to have prior to taking this course. If none, state none. (ex: ability to analyze historical text; prepare a lesson plan)

Additional Information
Complete the following 3 questions or attach a syllabus that includes this information. If a 400-level or dual level course, a syllabus is required.
Title and author of any required text or publications.

Major topics to be covered and required readings including laboratory and studio topics.

List any required field trips, out of class activities, and/or guest speakers.

Dr. Solihin will teach this as part of his existing teaching load.

This course addresses topics in parallel computer architectures, i.e. architectures that support parallel processing. The course overviews fundamental issues related to parallel processing: programming paradigms, correctness, and performance; and case studies of modern parallel systems.

This course is intended for:

  • First-year PhD students who are looking to build foundational knowledge in parallel computer architecture and parallel programming, as one major area of computer architecture. The topics covered in this course hopefully will enable them to read technical and research papers and understand more advanced concepts as well as understand the implications of various designs in parallel computer architecture.

  • First-year Master’s degree students who are looking to build broad knowledge in the area of parallel computer architecture and parallel programming.

  • Final-year undergraduate students who have taken basic computer organization course, and are looking to learn more advanced concepts in computer architecture, especially in the area of multiprocessor and multicore technology, as well as in parallel programming

  • Graduate students should take this course prior to taking the more advanced ECE 706 (Parallel Processing).

Student Learning Outcomes

By the end of the course, students in ECE 406/506 and CSC 506 will be knowledgeable in the following concepts in parallel computing/architecture:

  • Explain why parallel architectures are needed, and where and how they are used.

  • Compare and contrast different parallel programming models: shared memory (e.g. OpenMP) vs. message passing.

  • Describe and apply parallel programming constructs in software: locks, barriers, point-to-point synchronization

  • Describe and evaluate multiple parallelization techniques: loop level, task level, and algorithm level.

  • Identify correctness issues in parallel programs related to variable scope, synchronization points, and computation ordering.

  • Describe common performance bottlenecks related to loop transformations, thread scheduling, locality, page allocation, and false sharing.

  • Describe the memory hierarchy and organization for a parallel computer, in particular, cache organization, write policy (write-through vs. write-back), replacement policy.

  • Describe a bus-based multiprocessor architecture.

  • Describe cache coherence protocols on bus-based machines and evaluate their latency and bandwidth trade-offs.

  • Describe hardware support for synchronization primitives.

  • Define memory consistency.

  • Describe and evaluate  directory-based cache coherency on distributed shared memory machines.

  • Describe common interconnection networks in use today.

Students in ECE 506 and CSC 506 have these additional learning outcomes:

  • Apply multiple parallelization techniques to solve a parallel computing problem: loop level, task level, and algorithm level.

  • Implement multiple cache coherence and evaluate their relative performance and behavioral characteristics.

  • Compare and contrast different memory consistency policies, such as sequential consistency, processor consistency, release consistency, etc.

  • Evaluate trade-offs in the design and organization of memory hierarchies for parallel computers.

Evaluation MethodWeighting/Points for EachDetails
Quizzes10%Per module quizzes.
Homework10%406 students will have fewer problems or problems of reduced scope.
Project20%Machine Problems; 406 students will have problems of reduced scope.
Midterm30%Midterm Exam
Final Exam30%Final Exam
TopicTime Devoted to Each TopicActivity
Introduction1.5 weeksRead Ch. 1.
Parallel Programming Models0.5 weeksRead Ch. 2.
Parallel Programming Techniques2 weeksRead Ch. 3.
Correctness and Performance1.5 weeksRead Ch. 4.
Parallel Programming with Linked Data Structures0.5 weeksRead Ch. 5.
Introduction to Memory Hierarchy1 weekRead Ch. 6.
Coherence, Consistency, Synchronization0.5 weeksRead Ch. 7.
Bus-based Cache Coherent Multiprocessors2 weeksRead Ch. 8.
Synchronization1 weekRead Ch. 9.
Memory Consistency Model1 weekRead Ch. 10
Interconnection Network0.5 weeksRead Ch. 12
Distributed Systems1 week Read Ch. 11
mlnosbis 12/9/2016: Ready for ABGS Reviewers.

ABGS Reviewer Comments:
-Does the prerequisite apply to CSC 406, as well? Syllabus says that for ECE 406 "To enroll, you must have taken ECE 310 (Design of Complex Digital Systems). In Computer Science, an equivalent course may be CSC 312 (Computer Organization and Logic) or CSC 456 (Computer Architecture and Multiprocessors). Should the alternative courses be listed in CIM as well so that students know this before the course starts? RESPONSE: CSC prerequisites should be listed in the prerequisite field.
-The syllabus should be more definitive in listing the additional requirements for graduate students rather than the statement ""ECE/CSC 506 students may have more requirements/or they may have questions than ECE 406 students that pertain to the additional learning outcomes of ECE/CSC 506." It should be clearly stated as to how the 500-level differs from the 400-level.
bahler (Thu, 11 Feb 2016 01:15:14 GMT): Syllabus makes mention of "492 students". This document mentions "406 students".
lamarcus (Fri, 18 Nov 2016 21:31:28 GMT): Rollback: At instructor request and also for Approved Pending items: - Clarifying prerequisites: The items in this field all need to be codable in Peoplesoft, so ECE 310 is fine, but are there a series of courses that would translate to "sufficient knowledge of hardware design principles?" If not, that item can definitely go in the catalog description!- Adding a statement to the catalog description to the effect of "Credit is not allowed for more than one course in this set: ECE 406, ECE 506, CSC 406" etc to indicate that a student will not be able to take this course more than once for credit. This is already built into the system functionally, but the committee would like a written statement added in order to alert students.
Key: 1364